Whitepapers
System-on-Chip Design using Self-timed Networks-on-Chip
Self-timed NoC implementations combine the architectural benefits of a networking approach over a conventional bus hieraarchy, with the timing closure and power-management benefits of self-timed design. The result is a flexible, clockindependent solution to the complexity, power-management and timing closure problems of SoC interconnect in deep submicron VLSI systems.
click to download pdf version of the paper.CHAIN - A Delay-insensitive Chip Area Interconnect
by Bainbridge and Furber
The increasing complexity of System-on-Chip designs exposes the limits imposed by the standard synchronous bus. The authors propose a mixed system solution.
click to download pdf version of the paper.Future Trends in SoC Interconnect
by Steve Furber
Self-timed packet-switched networks are poised to take a major role in addressing the complex system design and timing closure problems of future complex Systems-on-Chip. The robust, correct-by-construction characteristics of self-timed communications enables each IP block on the SoC to operate in its own isolated timing domain, greatly simplifying the problems of timing verification. Design automation software can remove the need for expertise in self-timed design, enabling the on-chip interconnect to be treated as an additional IP block within a conventional (synchronous) design flow
click to download pdf version of the paper.