Frequently Asked Questions


Q: What is Silistix CHAINworks?
A: CHAINworks is a suite of EDA tools, that easily fits in your Customer Owned Tools (COT) flow, to create an application optimized on-chip interconnect. Using the CHAINworks tools, comprised of CHAINarchitect, CHAINcompiler, and CHAINlibrary, SoC designers can quickly configure, model, and implement an interconnect fabric that best fits the design goals of any SoC.


Q: What can Silistix CHAINworks do for me?
A: CHAINworks gives SoC designers the ability to reduce time to closure, design effort, and power consumption. Our globally asynchronous, locally synchronous, (GALS) methodology enables designers to easily integrate diverse IP blocks at multiple frequencies, in multiple clock domains. Significant power savings occurs by running these blocks at their natural frequency rather than an arbitrary multiple of a global system clock


Q: What are the key benefits of a CHAIN fabric?

A: The key benefits of CHAIN fabric are as follows:

  1. Lower overall power consumption due to data-driven switching and elimination of the system clock tree
  2. Faster time to market due to simpler timing closure
  3. Modular interconnect gives true plug-and-play SoC design
  4. Heterogeneous, unrelated clock domain support
  5. Radio Frequency noise reduction due to self-timed nature of the network

Q: How does CHAINworks fit into my existing design flow?
A: CHAINworks fits as an additional step in your existing COTs flow, and integrates into your design as another system module. Information from later stages of your flow can be fed back into CHAINworks to improve model accuracy, identify congestion, and provide improved design guidance.


Q: How, exactly, will CHAIN help me reach timing closure faster?
A: Silistix CHAINworks creates a self-timed network interconnect that always meets timing. The self-timed CHAIN network fabric is quasi-delay insensitive so the interconnect is not constrained by timing closure issues. This frees the designer to focus their efforts on closing individual IP blocks. Once all of the individual blocks have met timing, our GALS methodology ensures top-level timing closure, without extensive iterations.


Q: What's wrong with the synchronous busses we've been using for years?
A: While there is nothing wrong with synchronous bus technology, as SoC designs become more complex it becomes increasingly difficult to mange performance, power, and area constraints. As deep sub-micron effects predominate system performance, shared bus topologies become increasingly unable to cope with today’s complex designs. Typically these extra demands require dividing system level interconnects into multiple bus hierarchies across multiple clock domains, adding design time and effort. CHAINworks reduces the time and effort required to design and implement today’s complex SoCs. Our self-timed CHAIN technology allows point-to-point communication at true wire speeds without the limits of a global system clock.


Q: Don’t Network on Chip (NoC) solutions increase my die area?

A: To maximize concurrent performance some vendor solutions add significantly to the total system gate count and power consumption.

Silistix CHAINworks allows designers to create an application optimized interconnect that balances performance, area, and power consumption to fit your system requirements. While some sections of a CHAIN fabric can be larger than the simple busses they replace, the trade-offs between performance and area are comparable at a system level.


Q: How is CHAIN different from other NoC implementations?
A: Some NoC on-chip networks claim to be asynchronous, but use synchronous logic running at four times the system clock to achieve an independent clock domain. The Silistix CHAIN fabric is self-timed, and operates at the true wire speed of each link rather than the “worst-case” timing imposed by a system clock tree.


Q: How do CHAIN fabrics save on power consumption?
A: There are three major ways in which the Silistix CHAIN fabric reduces power consumption. First, a system clock tree often represents about 30% of the total power consumed by a conventional SoC. By pruning the system clock tree, CHAIN interconnects allow designers to reduce clock tree power. The second way CHAIN reduces power is by enabling designers to operate IP blocks at there natural operating frequency. Many I/O peripherals (UART, Ethernet MAC, USB, etc) operate with external timing, and do not benefit from a faster system or bus interface. Finally, low power operation is inherent in the self-timed nature of our interconnect logic. Unlike synchronous busses that force transitions on every clock cycle, the Silistix CHAIN fabric is data-driven and transistors change only when the data being transmitted changes, thereby conserving power.


Q: Does Silistix CHAIN networks support BIST?
A: The network incorporates some BIST support for core coverage of the interconnect, with test of the remaining components supported through scan using patterns generated by CHAINcompiler.


Q: How is scan insertion done with CHAIN?
A: Scan is used by breaking every feedback path and inserting scan-latches. Partial-scan variations on this scheme only break carefully chosen feedback paths


Q: Is it possible to guarantee performance using CHAIN?
A: In existing systems with multiple buses spanning multiple clock-domains and many synchronizers, guaranteeing absolute performance can be difficult as it depends on the activity of all traffic generating devices in the system. When such a system is migrated to a CHAIN fabric, validation of absolute performance becomes even more complex, but can be achieved through a similar approach of using behavioral and statistical models of the fabric and traffic generators. Typically it is simpler, faster and cheaper to allocate sufficient performance margin to allow straightforward estimation of performance.


Q: Will CHAIN work with my existing IP blocks?
A: The CHAIN fabric itself is bus-architecture independent, but it uses adapters to interface existing synchronous blocks with the network. Currently, AMBA network adapters are supported with CoreConnect and OCP adapters soon to follow.


Q: Does the Silistix fabric network apply to FPGA as well as standard cell designs?
A: Silistix CHAIN fabrics are currently targeted at standard cell SoC and ASIC designs. Research is underway to determine whether an FPGA implementation is practical given the fact that FPGA's are not well suited for self-timed logic.