Technology

Technology Overview
To be able to provide predictable NoC solutions that enable customers to readily accomplish their most complex designs, Silistix has developed breakthrough technology in several areas. These critical advances are combined in the CHAIN™ works product to tightly couple the three critical phases of a complex SoC design; Architecture, Logical design and Physical design. CHAIN™ works provides an aggregation of interactions that assure that all aspects of these critical stages in the creation of a complex chip share the right information at the right stages in the design process.

 Before CHAIN™ works

Without CHAIN™ works, the chip architect specifies communications requirements for all the system components as best they can. Best practices today use spreadsheet-based methods sometimes augmented with SystemC simulation, to estimate and track bandwidth requirements for each system component in the design.

The interface requirements are partitioned out in the sub-system specifications, then implemented in Verilog and synthesized. Physical design can then begin. The convergence between logical and physical design is getting more and more difficult with faster clocks and each successive deep submicron process node. Process variability and the increasing dominance of wires rather than gates on timing are making control of clock skew and design of the clock tree more and more critical. Integration of the system components, and confirming that the design as a whole can be physically implemented in a manner that meets functional requirements at the desired operating frequencies, is becoming more and more time consuming. This process is known as achieving timing closure. Only once this is done, can the architect confirm that the design actually meets the system requirements. If it does not, either the design specification has to be de-rated or the team must embark on a very lengthy design iteration cycle.

After CHAIN™ works

With CHAIN™ works, the architect specifies the communications requirements for the design in a high-level of abstraction description called Connection Specification Language (CSL). The design information captured in the CSL file is readily known at an early stage of chip design the connectivity matrix for the system components in the design, the data bandwidths required in each major system operating mode, and any other known requirements such as must meet latencies. CSL provides the architect a way to capture these interconnect requirements in a convenient and natural form that is not supported by any other common formats or standardized design languages today.

CHAIN™ works rapidly generates a NoC topology meeting these requirements, and provides Power, Performance and Area (PPA) numbers based on the characterization information for the NoC components used in the topology. In addition to checking network provisioning through static analysis, CHAIN™ works generates simulation models in SystemC or Verilog complete with a network performance validation testbench to verify the NoC performance with the network traffic defined in the CSL description.

CHAIN™ works also generates the Verilog netlist for synthesis. When available, system component placement information can be entered into CHAIN™ works, either in the CSL file, or by reading in common formats used by leading physical design tools. CHAIN™ works adjusts the network to allow for the physical placement of NoC components, and adjusts the structure of connections to span cross-chip distances as required. Some physical information, especially for system components of sub-systems being reused from a previous design, is often known at an early stage in the design cycle. Even incomplete information can make a big difference to the accuracy of early results. In the case that physical information was added into the CSL file, CHAIN™ works outputs a placed DEF format for the NoC, which can be used as a starting point for placement. In the case that a floorplan was read into CHAIN™ works, the placement of the NoC is added to the floorplan.

CHAIN™ works unique capability to simultaneously manage the NoC between the architectural, logical and physical design domains greatly shortens the design iteration time allowing early confirmation and continual re-confirmation at each design stage that the on-chip interconnect fully meets the system requirements, with predictable power and area costs. CHAIN™ works ability to speed the architectural, logical and physical design convergence, derived from the system-level connection requirements, is what Silistix terms Interconnect-Driven Design.

Silistix technical advances are concentrated in the following critical areas: