Silistix News Room
News Briefs
A Different Approach - EDN.com
Editor Graham Prophet looks at how Silistix applies asynchronous design to achieve the fastest possible performance and reduce power for SoC designs.
SoC Design Requires a New, Predictable Approach - Future Fab International
Design predictability key in alleviating major problems associated with the development of complex SoCs
Time's Up for Clock-Based Buses on Multicore Chips
Replacing a traditional bus interconnect with system with a clockless network provides several performance and design advantages for multicore processor chips.
SoC Schedules: Slip slidin' away
EE Times' Junko Yoshida ponders the current state of SoC designs: up to 89 percent of IC development projects miss their deadlines
Chip design lacks system predictability
We are at a crossroads in the semiconductor industry, where the difficulty in meeting chip design deadlines is not a lack of proper skills or mature EDA tools, but rather a more insidious demon.
Good embedded communications is the key to multicore hardware design success
Self-timed NoC interconnects can solve a lot of the problems with overloaded data buses.
Traffic management: a growing nightmare for SOC designers
Silistix addresses the challenges of traffic management with
predictable performance, power and area. Modeling at the architecture
level based on physical implementation details assures implementation
success.
Silistix Featured as a Top European Startup
The European Tech Tour today announced that 24 companies had been selected as the winners of its 2007 English Tech Tour, in which the country's most promising high growth, early- and expansion-stage technology companies stand to benefit from investment funding.
EE Times Lists Silistix as a Top Emerging Company
Semiconductor startups are the creative engines which drive the electronics industry because they develop state-of-the-art integrated circuits for next generation products and set the pace for semiconductor innovation. InsideChips is for entrepreneurs, investors, electronics executives, EDA tools marketers, silicon foundry sales executives, service providers and for executives or firms who wish to do deals with chip startups.