Overview

Silistix Network-on-Chip (NoC) solutions target complex applications where multiple functions converge on a single System-on-Chip (SoC).  These SoCs,  the engines that drive all of today's best-selling digital consumer electronics, now typically consist of multiple processors and many hundreds of millions of transistors.  Take smartphones for example.  Today's latest devices combine multiple wireless modems (3G/4G, WiFi, Bluetooth etc.) with GPS, camera, video recording and playback (soon with 1080p and 60fps), Flash, rendered graphics and MP3 audio.  As well as games and videos, we also expect to run all the email, internet and business applications we'd previously need a PC for, all on-the-go, with a battery life of up to a day's use time and many days standby.  Designing these SoCs is increasingly challenging, and unless radical new methods are adopted, the design cycle time (and hence time-to-market) greatly lengthens compared with the previous generation of chips. 

The biggest challenges SoC developers face which extend the design cycle time include managing chip complexity and obtaining predictable results throughout the design cycle.  Designers manage complexity first, through design re-use by integrating existing Intellectual Property (IP) wherever possible; and second, by designing new content from the highest level of abstraction possible.

Predictable results are increasingly challenging to obtain as existing Electronic Design Automation (EDA) tools struggle to cope with the increasing demands and greater variability of each successive deep-submicron silicon process node.  The smaller the process node, the greater the effect of the interconnecting wires on overall circuit performance, and the more difficult it is to confirm that the design can be physically implemented to perform with the required logical functionality at the required operating frequency.  Until this point of convergence of physical and logical domains at full operating frequency (known as timing closure) is found, the designer cannot estimate with any certainty the performance, power and area numbers for the design.  The choice of on-chip interconnect has a big effect on these challenges.  The SoCs for the current generation of smartphones are typically on 65LP process, and designers struggled with current methods to achieve timing closure.  The SoCs in design now are typically on 45LP process, and the drive for higher performance yet lower power means that 32nm or 28nm designs are just around the corner.  At these nodes, process variability and the effect of interconnect on overall performance increase greatly.  Designers need an on-chip interconnect solution that addresses these challenges while cutting overall chip design time and effort.

The Silistix CHAIN™ works solution helps designers to overcome their SoC design challenges and deliver strategic value for these markets. Silistix NoCs support all common IP interface protocols, such as AMBA AXI, AHB and APB, and OCP, to promote easy integration of customer IP blocks. Even when maximizing re-use of existing IP, the on-chip interconnect is one area that has to be designed more-or-less from scratch with each design. The CHAIN™ works toolset allows the NoC to be designed from a very high level of abstractions from a natural specification of the connection requirements. Through a combination of accurate modeling of NoC components for the process technology in use, and patented asynchronous techniques to span chip-level connections between blocks, Silistix eradicates timing closure problems and delivers predictable results for performance, power and area throughout the SoC design flow.

The benefits of the CHAIN™ works technology described above lead to significant business benefits for developers of these complex chips. Shorter cycle times and predictable results lead to faster time to market for initial designs and more rapid development of derivative designs (green arrows in figure above) compared with previous methods (blue arrows).

Contact us and let us help you to assess what Silistix Interconnect-Driven Design could do for your business.