Silistix CHAIN™ works provides for rapid iterations on critical decision points in the three key design steps for complex chips: Architectural Design, Logical Design and Physical Design. (see figure 1) Standard file formats and script languages are used to provide tight integration between CHAIN™ works and commonly used EDA tools for each of these design steps.
Figure 1
A unique advantage of the CHAIN™ works flow is that information is passed both forward and backward from standard EDA tools to assure that design decisions are made with the best possible information, and that those decisions are kept intact as the design progresses through steps further in the overall design process. For example, physical placement information that is used in making architectural decisions on the structure of the NoC is passed forward to the physical design in the form of floorplanning guidelines while the final placement of critical components in the overall system and the NoC is passed back to CHAIN™ works for a quick verification that the critical cross-chip distances within the final placements can still be managed with the unique distance spanning capabilities of the Silistix NoC. This critical verification step is very rapid, requiring only a few minutes to complete, while providing assurance that the overall system will function as defined in the CSL description of the system.
CHAIN™ works' ability to speed the architectural, logical and physical design convergence, derived from the system-level connection requirements and enabled by tight integration with standard EDA tools in all three steps, is what Silistix terms Interconnect-Driven Design. Contact Silistix for an analysis of the specifics of your design flow and the specific EDA tools being used.