CHAINworks

CHAINworks is a suite of tools for the design and synthesis of on-chip interconnect that fits directly into your existing design flow. The process of designing a predictable on-chip interconnect is as follows:

Step 1 - Design Entry

System Requirements captured in Connection Specification Language (CSL)
Use of implementation specific data provides predictable results for power, performance and area.
Uses "flat-bus" conceptual model with constraints on client connections

Step 2 - Use CHAINworks Tools

Use CHAINarchitect to explore CHAIN Interconnect topologies
- Synthesis of interconnect from CSL
- Delivers predictable and accurate results based on implementation details
- Reports / visualization simplify tradeoff analysis
- Capture initial floor plan estimates
Generate SystemC models of system for use in Electronic System Level (ESL) analysis and modeling - times and untimed models
Generate Verilog for simulation / implementation - behavioral models for simulation / synthesizable plus Hard Macro instantiation
Generates STA scripts
Generates P&R hints
Generate DFT vectors

Step 3 - Synthesis

Using existing synthesis tools

Step 4 - Static Timing Analysis (STA)

Uses STA scripts generated by CHAINworks
Using existing STA tools
If STA fails to go to Step 2

Step 5 - Place and Route (P&R)

Using existing Place and Route Tools
Use initial floorplan estimates from CHAINarchitect

Step 6 - Extraction and STA

Using existing extraction and STA tools
Uses STA scripts generated by CHAINworks

Step 7 - GDS II Out (Tape Out)

Send GDS II to fab and wait for samples

Products