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CHAINdesigner

CHAINdesigner is a graphical design tool used to specify topoligies and attributes of self-timed on-chip interconnect.

Using CHAINdesigner's familiar point-and-click, drag-and-drop interface you the can visually describe your CHAIN fabric using a simple palette or automatically using built-in heuristics.

Using CHAINdesigner you can:

• Place gateways
• Connect ports to clients
• Automatically or manually create a CHAIN topology
• Control the width of connections to manage area and performance tradeoffs (serial vs. parallel data transmission)
• Insert pipeline stages

The outputs of CHAINdesigner are:

• Behavioral Verilog suitable of input to any standard Verilog simulator
• System C suitable for input to any System C simulator
• Test Bench for simulation
• A constrained CHAIN netlist suitable for input to CHAINcompiler