Articles
Optimize Memory System Design For Multimedia Applications
Silistix' Dave Lautzenheiser & Agha Hussein discuss how the convergence of video and communications in inexpensive unified-memory architectures has made DRAM the most important and the highest-performance target in any system.
The Compounding Effect of Complexity on SoC Design & Predictability
Even with the best tools available, some SoC design trends are dramatically affecting predictability and therefore overall development cost.
A Different Approach - EDN.com
Editor Graham Prophet looks at how Silistix applies asynchronous design to achieve the fastest possible performance and reduce power for SoC designs.
SoC Design Requires a New, Predictable Approach - Future Fab International
Design predictability key in alleviating major problems associated with the development of complex SoCs
Time's Up for Clock-Based Buses on Multicore Chips
Replacing a traditional bus interconnect with system with a clockless network provides several performance and design advantages for multicore processor chips.
SoC Schedules: Slip slidin' away
EE Times' Junko Yoshida ponders the current state of SoC designs: up to 89 percent of IC development projects miss their deadlines
Chip design lacks system predictability
We are at a crossroads in the semiconductor industry, where the difficulty in meeting chip design deadlines is not a lack of proper skills or mature EDA tools, but rather a more insidious demon.
Good embedded communications is the key to multicore hardware design success
Self-timed NoC interconnects can solve a lot of the problems with overloaded data buses.
Traffic management: a growing nightmare for SOC designers
Silistix addresses the challenges of traffic management with
predictable performance, power and area. Modeling at the architecture
level based on physical implementation details assures implementation
success.
Silistix Featured as a Top European Startup
The European Tech Tour today announced that 24 companies had been selected as the winners of its 2007 English Tech Tour, in which the country's most promising high growth, early- and expansion-stage technology companies stand to benefit from investment funding.
EE Times Lists Silistix as a Top Emerging Company
Semiconductor startups are the creative engines which drive the electronics industry because they develop state-of-the-art integrated circuits for next generation products and set the pace for semiconductor innovation. InsideChips is for entrepreneurs, investors, electronics executives, EDA tools marketers, silicon foundry sales executives, service providers and for executives or firms who wish to do deals with chip startups.
Archives
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Title
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Source
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Date
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| OpenMic: Self-timed interconnect enables true IP reuse
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EE Times |
July 25, 2007 |
| Silistix Gets Silicon Valley Veteran Bruce Bourbon as New Board of Directors Chair
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D&R |
February 5, 2007 |
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Partnerships UK backs Silistix in $6M close to Series A
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EE Times |
January 16, 2007 |
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CHAIN works named among industry's top products of 2006
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EDN |
December 15, 2006 |
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Startups developing ES flow for self-timed interconnect
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EE Times |
July 20, 2006 |
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ARM, Silistix mimic braind for robot control
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Electronics Weekly |
July 20, 2006 |
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Self-timed Interconnect solution support AXI bus protocol
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EE Times |
July 17, 2006 |
| Silistix, Tensilica, Denali and Sci-worx team to produce world's first self-timed A/V chip
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EE Times |
June 27, 2006 |
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Silistx, Tensilica team on multi-core demo IC
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EE Times |
June 26, 2006 |
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Communication Nightmares Grow
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Electronic News |
May 25, 2006 |
| Silistix honored with submission in EDN's "Hot 100 Products of 2006"
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EDN |
December 15, 2006 |
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EE Times updates list of 60 emerging startups
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EE Times |
April 27 , 2006 |
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McGuffin out, Fritz in as Silistix CEO
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EE Times |
April 6, 2006 |
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David Fritz promoted to CEO of Silistix
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D & R Headline News |
April 6, 2006 |
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David Fritz promoted to CEO of Silistix - Company to leadership position in SoC methodology
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EDA Cafe |
April 5, 2006 |
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Self-timed interconnect startup joins OCP-IP
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EE Times |
February 13, 2006 |
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Silistix joins OCP-IP
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D & R Headline News |
February 13, 2006 |
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Self-timed interconnect network eases SoC Design
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Electronic Design |
February 2, 2006 |
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Startup supporting AMBA protocol
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EE Times |
January 30, 2006 |
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Silistix Self-Timed Interconnect Solution Supports AMBA Bus Protocol
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EDA Cafe |
January 30, 2006 |
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Silistix Self-Timed Interconnect Solution Supports AMBA Bus Protocol
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PR Newswire via Yahoo Finance |
January 30, 2006 |
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Silistix Self-Timed Interconnect Solution Supports AMBA Bus Protocol
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Sys-Con Media |
January 30, 2006 |
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Silistix provides novel solution to SoC Integration
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SoC Central |
January 17, 2006 |
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Silistix launches self-timed interconnect development tools
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Embedded Star |
January 17, 2006 |
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Silistix announces CHAIN works for self-timed interconnect design and synthesis for SoSs
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Full Press, Italy |
January 17, 2006 |
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Silistix introduces tools to take asynchronous design mainstream"
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EDN |
January 16, 2006 |
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Asynchronous Tools Coming in Q2, Says Silistix
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EE Times |
January 16, 2006 |
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Tool Suite Rolls for Async Logic
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EE Times |
January 16, 2006 |
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Silistix Announces CHAIN works for Self-timed Interconnect Design and Synthesis for SoCs
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SoC Central |
January 16, 2006 |
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Silistix Announces CHAIN works for Self-timed Interconnect Design and Synthesis for SoCs
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EDA Cafe |
January 16, 2006 |
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Silistix Announces CHAIN works for Self-timed Interconnect Design and Synthesis for SoCs
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D & R Headline News |
January 16, 2006 |
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Viewpoint: Taming the Interconnect Beast
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Chip Design |
January 9, 2006 |
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On-chip nets look to rewire next-gen ICs
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EE Times |
December 26, 2005 |
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On-chip nets look to rewire next-gen ICs
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D & R Headline News |
December 26, 2005 |
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Startup aims to reduce power & design efforts
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IQ Online |
December 23, 2005 |
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Startup unveils clockless SoC interconnect
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Embedded.com |
December 22, 2005 |
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Silistix pushes asynchronous design
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Electronics Weekly |
December 21, 2005 |
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Startup Silistix Overcomes ''Slow Wire'' Communications Problems of Complex SoCs
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SoC Central |
December 21, 2005 |
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Startup Silistix Overcomes ''Slow Wire'' Communications Problems of Complex SoCs
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Design and Reuse |
December 19, 2005 |
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Startup unveils clockless SoC interconnect
| EE Times |
December 19, 2005 |
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Startup Silistix Overcomes "Slow Wire" Communications Problems of Complex SoCs
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EE Product Center |
Decdmber 19, 2005 |
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IP and EDA startup wants to make SoCs asynchronous"
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EDN |
December 19, 2005 |
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Startup Silistix Overcomes ''Slow Wire'' Communications Problems of Complex SoCs
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Fullpress |
December 19, 2005 |
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NoC, NoC, NoCing at Heaven's Door: Beyond MPSOCs"
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EDN |
December 8, 2005 |
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EE Times updates list of 60 emerging startups
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EE Times |
November 11, 2005 |
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EE Times updates list of 60 emerging startups
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EE Times |
April 29, 2005 |
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Intel backs Manchester self-timed logic startup
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EE Times |
April 18, 2005 |
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Asynch pioneer looks to explore the brain
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EE Times |
April 11, 2005 |
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No Clock, no Bus, no Sweat
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IEEE |
September, 2004 |
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