Silistix enables leading semiconductor companies to get their designs right the first time using predictable NoC (Network-on-Chip) solutions for managing chip complexity. In today's multi-processor systems-on-chip (MPSoCs), subsystems must communicate in parallel, and traditional on-chip buses and crossbars can no longer handle the traffic. Moreover, as design size, clock speeds and process variability issues increase, getting the design implementation to match the design intent (commonly known as design closure) is becoming exceedingly difficult and time-consuming. Current interconnect methods are a big part of that problem and designers are turning to on-chip networks as the solution.
The Silistix CHAIN™ works tool suite and IP library lets you drive the design from the interconnect requirements, by synthesizing true GALS (Globally Asynchronous Locally Synchronous) NoC interconnects, which simultaneously manage both complex on-chip communication needs and deep submicron design closure issues. The up-front predictability of the NoC interconnect's power, performance and area results from Silistix' careful design and characterization of the NoC's configurable components in the latest process technologies. Silistix predictable NoC solutions are utilized today by companies producing smartphones, ultra mobile computing, DTV, DVR and other mobile, audio and video products.
10/5/2009 - Peter Clarke's EE Times List of 60 Emerging Startups, first published in April 2004, has been updated to version 9.0, highlighting the hottest new companies and technologies.
©2009 Silistix, Inc. and Silistix, Ltd. All rights reserved. Company Number: 4744791
